Large electrical devices such as supercomputers of the type manufactured by Cray Research, Inc., the assignee of the present invention, are constructed of a large plurality of integrated circuits. In the prior art, integrated circuits are typically fabricated on wafers which are cut into individual integrated circuit chips and packaged within hermetically sealed ceramic or plastic packages. The signal and power lines from the integrated circuit chips are brought out to the pins of the packages by means of leads attached to the bonding pads on the integrated circuit chips. The chips are then used to form larger circuits by interconnecting the integrated circuit packages by means of a printed circuit (PC) board. The circuit board contains interconnect lines or foils on the surfaces of the circuit boards or within planar layers. The circuit board is populated with integrated circuit packages which are soldered to plated via holes or on surface mounted pads on the circuit board. The soldering process forms an electrical and mechanical connection between the integrated circuit package and the circuit board.
To form larger circuits, circuit boards populated with integrated circuit packages are interconnected by a variety of connectors, wires, or cables. The physical arrangement of the circuit boards in relation to one another is also accomplished in a wide variety of configurations. One popular high-density interconnect technique is to stack the circuit boards in a sandwiched relationship to one another and electrically interconnect the circuit boards with interboard connectors. This packing technique achieves a fair amount of packing density, limited by the interboard spacing requirements of heat dissipation and connector spacing.
The aforementioned technique of forming larger circuits from individual integrated circuits using integrated circuit packages and circuit boards results in limited packing density of the actual area which is used for electrical circuits. The actual integrated circuit chips themselves are typically smaller than one-tenth of a square inch, and in total would cover only 10-20 percent of the board area. However, due to the inefficiencies of packaging of integrated circuit chips and connecting the integrated circuit chips to the circuit boards, it is difficult or impossible to increase the packing density on circuit boards to improve speed or spacing advantages. In addition, interboard spacing is limited by the area consumed by the integrated circuit packages and inter-board connects. This limited packing density limits the inter-circuit signal speed due to the long propagation delays along the long interconnect lines.